VMOS, UMOS technology simulation

VMOS, UMOS ("V"-groove-metal-oxide-silicon) transistors drain and gate are formed in the groove of "V" or "U" form. Expanding channel area, therefore VMOS and UMOS structures may use in the power chips. Using VMOS, UMOS is saving 40% free space than using NMOS technology. Nanostructures dimensions are very small, so it is important to keep pn junction in a right depth, in the all semiconductor manufacturing technological process. Analyzing influence to forming structure of each technological operation is used mathematical simulation program SUPREM IV. VMOS and UMOS technological operation was simulated in micro and nano level