Built-in self test and a VLSI stack-frame reduced-instruction set computer (RISC) architecture

The authors describe the construction of the SF2000 VLSI stack-frame RISC computer (a design based on the successful SF1 computer) and discuss the advanced methods, such as random pattern testing and design partitioning aids, used in the construction of the on-chip BIST (built-in self test) hardware in this three-chip computer. The SF2000 CPU chip will contain architectural elements such as a 2-way set of associative instruction cache, a data cache, and on-chip provisions to use the SF2000 as a computing element in a multiprocessing environment. The testability measures included on-chip will emphasize random-pattern testing, design partitioning, and concurrent memory testing with measures of their costs and effectiveness for future applications, such as larger VLSI and WSI circuits. Some methods which reduce the overhead of BIST designs without degradation of the test coverage of faults are also described. A 8×8 mm VLSI circuit in 1.2 micron double-metal CMOS technology and approximately 300000 transistors mounted in a 224 pin grid array package, is envisaged