Synthesis of concurrent hardware structures

A short overview is given of the architecture of a hardware synthesis system and its immediate data structure called the demand graph. Furthermore, two structural synthesis methods are described. The first method performs a scheduling, module selection, and allocation separately. The second performs these operations simultaneously by dynamic programming. Both methods assume fully clocked systems throughout. They allow trading space for speed by using all possible concurrency present in the demand graph representation. Some results are given and the applicability of this approach to VLSI structures is discussed.<>