TDTL architecture with fast error correction technique

A new technique for fast error correction of the TDTL (time delay digital tanlock loop) is proposed. The technique is based on early comparison of the input signal frequency with that of the loop filter output. The result of this comparison is then used to select an optimum value for the loop filter output. This technique eliminates the need for continuously changing the loop filter coefficient. The major advantages of the proposed technique are a reduction in the complexity of the adaptive TDTL structure and an improvement in the loop acquisition time. The performance of the proposed system was tested using an FSK input signal and the results indicate enhanced performance compared to the conventional TDTL system.