An on-chip parallel memory architecture for a stereo vision system

This paper presents a novel parallel System-on-Chip (SoC) memory architecture for a stereo vision system as required in 3D TV applications. It allows for a parallel access to all pixels located in a chosen window of the image. Using this architecture a complete window refresh on each clock cycle is possible, which can be used to increase the depth range of a stereo vision algorithm. This architecture is fully scalable and parameterizable to allow for custom SoC implementations, as well as rapid prototyping on FPGAs. Hardware resource utilization for different processor window size configurations is compared based on FPGA logic element use.