A comprehensive analyzer for the JIAWG high speed data bus

Author

Archer, H.S.

Author_Institution

Lockheed Sanders Co., Atlanta, GA, USA

fYear

1990

fDate

21-25 May 1990

Firstpage

174

Abstract

The author explains the HSDB (high speed data bus) protocol, describes the HSDB-A (high-speed data bus analyzer) hardware, and presents HSDB-A operation from the user´s point of view. The HSDB provides 50 Mb/s maximum bandwidth, adequate throughput, and excellent fault recovery characteristics. The HSDB serves as a mission avionics bus, coordinating processes among integrated racks. To debug systems interconnected by the HSDB, engineers need a comprehensive support tool that can monitor the bus, maintain bus performance statistics, selectively capture bus traffic on error or trigger conditions, emulate nonexistent terminals, and stress the bus to the specification limits. The HSDB-A fulfils this need

Keywords

aerospace computing; aircraft instrumentation; computer interfaces; fault tolerant computing; military computing; military equipment; protocols; 50 Mbit/s; JIAWG high speed data bus; Lockheed; US Air Force; computer interfaces; fault recovery characteristics; high-speed data bus analyzer; integrated racks; mission avionics bus; protocol; Aerospace electronics; Bandwidth; Condition monitoring; Data analysis; Error analysis; Hardware; Maintenance engineering; Protocols; Stress; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace and Electronics Conference, 1990. NAECON 1990., Proceedings of the IEEE 1990 National

Conference_Location

Dayton, OH

Type

conf

DOI

10.1109/NAECON.1990.112762

Filename

112762