NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGAS

Author

Sidiropoulos, H. ; Siozios, K. ; Soudris, D.

Author_Institution

Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece

fYear

2010

fDate

12-15 Dec. 2010

Firstpage

527

Lastpage

530

Abstract

A novel framework for supporting architecture-level exploration for heterogeneous FPGA devices is introduced. This framework, named NAROUTO, is based on open-source tools in order to support further extensions and improvements. As compared to previous works, the introduced framework provides higher flexibility for application implementation, while it can also evaluate power/energy consumption. Experimental results prove that NAROUTO leads to significant area, power (about 82%) and performance (about 46%) improvements, as compared to existing solutions.

Keywords

field programmable gate arrays; low-power electronics; public domain software; technology CAD (electronics); NAROUTO framework; architecture-level exploration; energy consumption; field programmable gate array; heterogeneous FPGA device; open-source framework; power consumption; Benchmark testing; Encryption; Field programmable gate arrays; Random access memory; CAD Tool; Exploration Framework; FPGA;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Conference_Location

Athens

Print_ISBN

978-1-4244-8155-2

Type

conf

DOI

10.1109/ICECS.2010.5724565

Filename

5724565