BIT-width exploration over 3D architectures using high-level synthesis

The interface between storage and processing has always been one of the main bottlenecks to the performance and energy efficiency in embedded system design. In this paper we are exploring the potential to increase the bandwidth through this interface by increasing the number of physical connections. This option becomes available using 3D stacking technologies. Our aim is to evaluate the power efficiency of a wider memory interface at the level of the complete system, including the memory, the interface circuitry itself and the processing elements. We want to understand whether this additional bandwidth can be efficiently utilized by the processing elements and enable an overall lower power and higher throughput solution compared to state-of-the-art system implementations.