FPGA implementation of the guided scrambling line coding technique

The guided scrambling (GS) line coding technique was introduced by Fair, Grover, Krzymien, and MacDonald (1991) as a novel mechanism to ensure that binary transmitted sequences exhibit desirable line code characteristics. We describe a field programmable gate array (FPGA) implementation of GS. The system accommodates code words of up to 32 bits in length, with one or two augmenting bits per word. It permits specification of any scrambling polynomial with degree less than or equal to 32, and through the choice of two code word selection mechanisms, can be optimized for either high transition density or minimization of low frequency content. The system is used to verify theoretical expectations for the power spectral density of the encoded stream for various scrambling parameters, and to confirm expected trends in the statistics of encoded sequences for code configurations whose theoretical analysis is impractical