Title :
A 65nm CMOS fully integrated 31.5 dBm triple SFDS Power Amplifier dedicated to W-CDMA application
Author :
Luque, Y. ; Deltimple, N. ; Kerhervé, E. ; Belot, D.
Author_Institution :
IMS Lab., Univ. of Bordeaux, Talence, France
Abstract :
This paper presents a 65nm CMOS-Power Amplifier (PA) designed for UMTS standard. It is based on a triple Stacked Folded pseudo-Differential Structure (triple SFDS) power stage and a differential cascode driver stage. The PA provides 31.5 dBm maximal output power (Pmax) with 20% of maximal power added efficiency (PAEmax) at 1.95 GHz. The linear gain is 37 dB and the compression point (OCP1) is 29.5 dBm. In order to fulfill the W-CDMA requirements, the PA respects the ACLR requirements until 23 dBm.
Keywords :
3G mobile communication; CMOS integrated circuits; code division multiple access; power amplifiers; CMOS-power amplifier; UMTS standard; W-CDMA requirements; compression point; differential cascode driver stage; size 65 nm; stacked folded pseudodifferential structure power stage; BiCMOS integrated circuits; CMOS integrated circuits; 65nm CMOS technology; Cascode; PA; Triple SFDS;
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Conference_Location :
Athens
Print_ISBN :
978-1-4244-8155-2
DOI :
10.1109/ICECS.2010.5724582
