Short-circuit energy dissipation model for sub-100nm CMOS buffers

A considerable part of the energy dissipation in CMOS buffers is due to short-circuit currents. In this paper, an accurate, analytical and compact model for this part of energy, i.e. the short-circuit energy dissipation, is presented. The model is based on closed-form expressions of the CMOS inverter output waveform, which include the influences of both transistor currents and the gate-drain coupling capacitance. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100nm devices, with an extension for varying transistor widths. The resulting energy model accounts for the influences of input voltage transition time, transistors´ sizes, device carrier velocity saturation and narrow-width effects, gate-drain and short-circuiting transistor´s gate-source capacitances, and output load. The model has been validated for a 90-nm CMOS technology, for different input transition times, capacitive loads & inverter sizes. The results show very good agreement with BSIM4 HSPICE simulations.