A study on layout quality of automatic generated cells

Breaking-through algorithms have been proposed in the latest years enabling the new paradigm of library-free automatic layout synthesis. Library-free synthesis is known to achieve a huge reduction in the number of transistors required to implement a circuit, reducing leakage power consumption. On the other hand, automatic-generated cells are expected to have a larger area than designed-by-hand ones. In this paper we evaluate the layout quality of an automatic generated cell library by ASTRAN, showing that even reducing the set of cells to the ones available in a commercial cell library, the cells generated by our tool gives a better result than the library ones. Our experiments suggests that, although the automatic generated cells layout is less dense, therefore having larger cell areas, timing and power are similar and input capacitances are smaller. Those characteristics result in a design with a speed increased by 12% in average and with a 24% in average smaller power consumption in our test cases.