A low-noise wide range delta-sigma frequency synthesizer for DTV broadband

Author

Liao, Te-Wen ; Su, Jun-Ren ; Hung, Chung-Chih

Author_Institution

Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2010

fDate

12-15 Dec. 2010

Firstpage

667

Lastpage

670

Abstract

The proposed low noise wide frequency range Phase Loco Loop (PLL) proposed in TSMC 0.18-um CMOS technology is developed for DTV broadband. It incorporates a Extended Multi-band Ring Voltage Control Oscillator (VCO) to enhance the frequency selection range of the conventional Multi-band Ring VCO accomplishing a wide frequency range and better phase noise PLL. This frequency synthesizer is measured the phase noise of - 97.1dBc/Hz at 3MHz offset frequency and reference spurs below - 69.78dBc at 36MHz offset. The VCO gain K_vco (73MHz/V~328MHz/V) is improved by using the Extended Multi-band Ring VCO obtaining a better phase noise performance than the conventional Multi-band Ring VCO structure.

Keywords

CMOS integrated circuits; digital television; oscillators; phase locked loops; voltage control; CMOS technology; DTV broadband; PLL; TSMC; frequency 3 MHz; frequency 36 MHz; low-noise wide range delta-sigma frequency synthesizer; multiband ring VCO structure; multiband ring voltage control oscillator; phase loco loop; size 0.18 mum; Digital TV; Frequency modulation; Frequency synthesizers; Time frequency analysis; Voltage-controlled oscillators; Σ -Δ modulator; PLL; Synthesizer; VCO;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Conference_Location

Athens

Print_ISBN

978-1-4244-8155-2

Type

conf

DOI

10.1109/ICECS.2010.5724600

Filename

5724600