A 3.2Gbps single-ended receiver using self-reference generation technique for DRAM interface

A 3.2 Gbps single-ended receiver using self-reference generation technique for DRAM interface is designed by using a 0.18 μm CMOS process. A multi-drop single-ended signaling system has limited bandwidth because of both inter-symbol interference (ISI) and reference voltage noise. In order to recover the data without using the equalizer and the reference line, the self-reference generation technique is proposed. The single-ended receiver generates the reference voltage by using the previous bit for each bit. The circuit occupies 140 × 120 μm² and dissipates 40 mW at the supply voltage of 1.8V when 3.2 Gbps of data is transmitted over the channel with 18.55-dB loss at the frequency of 1.6 GHz.