A high performance full pipelined arquitecture of MLP Neural Networks in FPGA

This paper presents an architecture for a FPGA based implementation of a Multilayer Perceptron Artificial Neural Network (ANN). The proposed architecture aims to support the implementation of large ANNs in FPGA concerning with the area reduction, interconnection resources and area/performance trade-off. The proposed architecture uses log₂ m adders for an ANN with m inputs. An ANN whose topology is 256-10-10 could reach a speed-up of 36 times compared to a conventional software implementation.