An application specific NoC mapping for optimized delay

This paper presents a delay computing-model for a 2D-mesh worm hole based NoC architecture that is a widely used topology structure in NoC design. The model captures the core´s message sending probability, packet length and the contention of link in the communication. The different solutions of core´s mapping onto NoC architecture will cause different average delay and a genetic algorithm, which is based on the delay model, can automatically provide an approximately optimal mapping lor large scale NoCs. The algorithm aims to achieve a minimum NoC average delay. Experimental results for random traffics and various NoC sizes show that an average approximately 20% reductions in the execution time than random mapping