CMOS leakage power at cell level

Author

Mendoza, R. ; Ferre, Antoni ; Balado, Luz ; Figueras, Jaume

Author_Institution

Departament d´Enginyeria Electronica, Univ. Politecnica de Catalunya, Barcelona

fYear

2006

fDate

5-7 Sept. 2006

Firstpage

194

Lastpage

199

Abstract

Leakage power consumption in nanometric CMOS circuits is growing at exponential rate due to the aggressive scaling trends of channel lengths, gate oxide thickness and doping profiles. In this paper the analysis and characterization of leakage currents and the corresponding leakage power is studied at cell level. A characterization methodology is discussed and applied to inverter, NAND and NOR cells using the Berkeley predictive technology model BPTM for BSIM 4.50 and HSPICE. The simulation results for 65, 45 and 32nm CMOS performed in these cells show the high dependence of leakage power on the circuit state and the increasing impact of gate leakage on the variability of the total leakage of the cell

Keywords

CMOS logic circuits; logic design; nanoelectronics; 32 nm; 45 nm; 65 nm; BSIM 4.50; Berkeley predictive technology model; CMOS leakage power; HSPICE; NAND cells; NOR cells; cell level; channel lengths; doping profiles; gate leakage; gate oxide thickness; inverter; leakage currents; leakage power consumption; nanometric CMOS circuits; CMOS technology; Circuit simulation; Doping profiles; Energy consumption; Gate leakage; Inverters; Leakage current; Predictive models; Semiconductor device modeling; Semiconductor process modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on

Conference_Location

Tunis

Print_ISBN

0-7803-9726-6

Type

conf

DOI

10.1109/DTIS.2006.1708658

Filename

1708658