Accumulator - based compression in symmetric transparent RAM BIST

Symmetric transparent BIST has been proposed as a means to skip the signature prediction phase during RAM testing (required in traditional transparent BIST), therefore achieving significant reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compression is performed using single input shift registers (SISRs, for bit-organized memories) or multiple input shift registers (MISRs, for word-organized memories) whose characteristic polynomials are modified during testing. In this paper the authors propose the utilization of accumulator modules for output data compression in symmetric transparent BIST for RAMs. It is shown that in this way both the hardware overhead and the complexity of the controller are considerably reduced