Digital cochlea model implementation using Xilinx XC3S500E Spartan-3E FPGA

An FPGA-based design of an electronic cochlear model is presented with the target FPGA being the Xilinx XC3S500E from the Spartan-3E family of devices. The design adopted consists of the traditional cascade of 2^nd order IIR low-pass filter stages tuned at frequencies following an exponential distribution, covering the human auditory range from 20 Hz to 20 KHz. Filter stages within the implementation employ dual fixed-point arithmetic and make use of the FPGA´s dedicated on-board hardware multiplier blocks for their computations. Such an approach for the implementation of the filters´ transfer function leads to the use of a time-division multiplexed scheme for the realization of the 24-stage filter chain designed, in view of limited FPGA hardware resources. Furthermore, a design for an ADC interface module using the Spartan-3E Starter Kit Board´s analogue capture circuit is presented to feed audio signals to the model.