A true zero-load stable CMOS capacitor-free low-dropout regulator with excessive gain reduction

External capacitor-free low-dropout regulators (LDO) are popular power management modules within integrated circuits (IC) for space-limited, low Bill-of-Material (BoM) applications. Conventional Miller pole-split based CMOS capacitor-free LDOs, however, suffer from zero-load oscillation, and shortcut solution such as using “stay alive” output current degrades the power efficiency. The purpose of this paper is to solve the oscillation problem without sacrificing efficiency, and a true zero-load stable (TZLS) design with excessive gain reduction is proposed. Two otherwise identical, 2.5-5 V to 2.3 V, 0-100 mA capacitor-free LDOs are designed and implemented in ON Semi 0.5 μm CMOS process, one using the conventional method, and the other using the proposed design. Though both methods are effective when “stay alive” current is available, only the proposed LDO remains stable when “stay alive” is removed under tighter efficiency requirement. This research enables CMOS capacitor-free LDOs to be truly robust and power efficient, ideal for future “green” electronic products.