A digitally controlled linear voltage regulator in a 65nm CMOS process

This paper presents a fully digitally controlled low dropout linear voltage regulator (LDO). It is implemented in a 65 nm low power CMOS process. The input voltage range covers 3 V to 5 V while the output voltage is 2.87 V with a nominal load of 150 mA. The digital controller was implemented using VHDL, automated synthesis- and place & route tools. The synchronous controller is assisted by an asynchronous gain adjustment circuit. It will be shown, that the proposed LDO can compete with the performance of analog solutions and at the same time it can exploit the advantages of its digital implementation.