SRAM dedicated PCMs for leakage characterization in nanometer CMOS technologies

Leakage currents are of major concern in nanometer technologies. To address this issue, it is essential to have a good understanding of all leakage contributors, very soon during the new technology development step. This paper presents our methodology to accurately characterize leakage in SRAM cells, while keeping same environment of a product. Process control monitors, containing different structures to measure sub-threshold, gate, gate induced drain and junction leakages, in each SRAM bit-cell transistor, are described. Other structures are used to quantify the impact on leakage of edge effects and strap locations. Presented design and measurement methodology allows a separate characterizing of each leakage contributor; in order to optimize consumption in chips using ATMKL 130nm CMOS technology