High speed multistage fuzzy hardware architecture for fuzzy logic control

This paper presents the design of a High Speed Multistage Fuzzy Hardware (HSMFH) architecture for fuzzy logic control. In multistage fuzzy rules, there are input, intermediate, and output variables. The intermediate variable is found in the then-part of the current inference stage and in the if-part of the next stage. Traditionally, the then-part evaluation takes more inferring time. Our approach to resolve the problem is to pre-compute the fuzzy set operations of the intermediate variables without information loss. In addition, to accelerate the inference speed, only the active fuzzy set operations are inferred in If-module and Then-module by using the access control (like DMA). By using the simulation example with 294 fuzzy rules (245 rules in the first stage and 49 rules in the second stage,) the HSMFH takes 128 clocks with the pre-computation technique for an inference cycle. In other words, in one clock, the HSMFH can infer 2.30 fuzzy rules with the precomputation technique