Speeding up simulation time in EEPROM memory designs

This paper presents an efficient technique to decrease simulation lime of EEPROM memory arrays. This technique is based on the complexity reduction of an existing compact EEPROM model. This original model is unsuitable when dealing with large memory arrays simulations. To overcome this limitation, the authors propose two alternative models which allow reducing time and memory space overheads when compared to the compact model. The first EEPROM model (level 1). is as simple as possible and provides fast simulation time. The second model (level 2) is a compromise between the compact model and the level 1 model. We also present simulation time results using these different models within memory arrays