New conception and algorithm of allocation mapping for processor arrays implemented into multi-context FPGA devices

In the paper authors present new concept of realization of algorithms with regular graphs of information dependencies, in form of systolic arrays realized in multi-context programmable devices. Processor matrix efficiency depends on both allocation and schedule mapping. Authors use evolution algorithms and constraint programming to determine allocation mapping and optimize runtime of set algorithm. Authors compared the runtime of Cholesky´s algorithm for banded matrices in which the new concept has been used with ones obtained by use of linear and non-linear allocation mapping for processor matrix.