Design of 4-bit parallel sub-sampling A/D converter for IR-UWB receiver

Author

Wang, Shenjie ; Hong, Zhiliang

Author_Institution

Dept. of Microelectron., Fudan Univ., Shanghai, China

fYear

2010

fDate

12-15 Dec. 2010

Firstpage

1049

Lastpage

1052

Abstract

This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband (IR-UWB) receiver with the sampling rate of 2.112 GS/s. The ADC´s specifications are optimized at the system level. Two parallel channels help to achieve high conversion speed and low power consumption. To tackle the problem of clock mismatch between the channels, a twice sampling front end is used. An improved averaging termination technique using intended asymmetric spatial filter response is proposed. This design is simulated in a 0.13 μm CMOS technology with 1.2 V power supply. Simulation results show a 26 dB SNDR in 4.8 GHz bandwidth with 36 mW power consumption and the Figure of Merit (FOM) is 0.24 pJ/step.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; integrated circuit design; radio receivers; spatial filters; ultra wideband communication; ADC specifications; CMOS technology; IR-UWB receiver; bandwidth 4.8 GHz; clock mismatch; dual-channel analog-to-digital converter; improved averaging termination technique; impulse radio ultrawideband receiver; intended asymmetric spatial filter response; parallel subsampling A-D converter; power 36 mW; sampling front end; size 0.13 mum; voltage 1.2 V; Decoding; ADC; averaging; comparator; sampling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Conference_Location

Athens

Print_ISBN

978-1-4244-8155-2

Type

conf

DOI

10.1109/ICECS.2010.5724695

Filename

5724695