Analysis of parasitic effects of small-outline packages for high-frequency integrated circuits

Author

Zhai, Chen ; Dawood, Muhammad

Author_Institution

Klipsch Sch. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM, USA

fYear

2010

fDate

12-15 Dec. 2010

Firstpage

1072

Lastpage

1075

Abstract

This study reports the packaging effects of a small-outline package (SOP) on overall electrical characteristics of RFICs. The parameters of an equivalent coupled-π model circuit are extracted from simulated S-parameters at low frequency. These parameters are then optimized over the desired frequency range for better accuracy. To verify the obtained circuit model, the tuning characteristic of a voltage controlled oscillator (VCO) was tested. The circuit is fabricated using a 0.5 um N-well CMOS process, and packaged in a 28-lead SOP plastic package. Experimental results are shown to closely match the simulation results.

Keywords

CMOS integrated circuits; S-parameters; integrated circuit packaging; plastic packaging; radiofrequency integrated circuits; voltage-controlled oscillators; N-well CMOS process; RFIC; VCO; equivalent coupled-π model circuit; high-frequency integrated circuits; parasitic effects; plastic package; simulated S-parameters; size 0.5 mum; small-outline packaging; voltage controlled oscillator; Frequency control; Frequency measurement; Inductors; Lead; Microwave FET integrated circuits; Scattering; Wires; RFIC; SOP; equivalent circuit; lead-frame; packaging effect;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Conference_Location

Athens

Print_ISBN

978-1-4244-8155-2

Type

conf

DOI

10.1109/ICECS.2010.5724701

Filename

5724701