Title :
An FPGA hardware implementation of the Rijndael block cipher
Author :
Dhoha, Chorfi ; Ben Othman, Slim ; Ben Saoud, Slim
Author_Institution :
LECAP-EPT /INSAT
Abstract :
In this paper, we present a hardware implementation of an Advanced Encryption Standard (AES) Rijndael (128-bit block and 128-bit key) using Xilinx development tools and Spartan FPGA circuits. All the modules in this core are described by using VHDL language. The developed Rijndael core is aimed at providing sufficient performance with good area efficiency. In fact, the encryption/decryption data path operates at 29,45MHz resulting in a throughput of 289,98 Mbits per second for the encryption and 157,1 Mbits per second for decryption. Encryption/decryption circuit will fit in one Xilinx Spartan XC2S600E circuit taking approximately 87% of the area (6068 Slices)
Keywords :
field programmable gate arrays; hardware description languages; logic design; 1 Mbit/s; 128 bit; 157 Mbits/s; 289 Mbits/s; 29 MHz; 45 MHz; 98 Mbits/s; Advanced Encryption Standard; FPGA hardware implementation; Rijndael block cipher; Spartan FPGA circuits; VHDL language; Xilinx Spartan XC2S600E circuit; Xilinx development tools; encryption/decryption circuit; Algorithm design and analysis; Application specific integrated circuits; Cryptography; DH-HEMTs; Field programmable gate arrays; Hardware; NIST; National security; Standards development; Throughput;
Conference_Titel :
Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on
Conference_Location :
Tunis
Print_ISBN :
0-7803-9726-6
DOI :
10.1109/DTIS.2006.1708717
