A novel scalable spiking pixel architecture for deep submicron CMOS technologies

In this paper, the authors propose a scalable spiking pixel architecture for deep submicron CMOS technologies. The proposed pixel architecture uniquely combines counting and memory functions into a single compact circuit, providing for in-pixel storage capability; in-pixel analog-to-digital conversion and random read-out of digital pixel values. Pixel fill-factor is better than 15% for a 50times50mum pixel fabricated using AMI 0.35mum CMOS technology. Reported experimental results validate the proposed spiking pixel architecture for the next generation of deep submicron silicon processes