A spatially reconfigurable fast differential interface for a wafer scale configurable platform

This paper presents an interface that is spatially programmable and that was designed to support fast differential signaling on a novel reconfigurable CMOS wafer-scale platform for electronic system prototyping. The device called WaferIC has a sea of tiny openings on its surface to adapt to the contact type, size, spacing and alignment of external integrated circuit components. The physical and electrical constraints of the needed wafer-scale differential configurable system are described, and an architecture is proposed for transmitting Current Mode Logic (CML) differential signals between two different integrated circuits deposited on the WaferIC surface. A small piece of the wafer scale active substrate has been implemented into a test-chip using a mature 0.18 μm CMOS technology. Post layout simulations show that under normal conditions, the configurable differential link can operate up to 2.5 Gbps.