SiP technologies: perspectives and challenges

The SiP (System-in-Package) technologies are becoming an important part of the semiconductors, and likely continue to grow in the future, following the market demand in portable applications, such as mobile phones or laptop computers, where the size and the power consumption represent the two major factors for a successful implementation. This paper starts with a brief introduction to the market trends, followed by a description of the various technologies involved: silicon-based, laminate-based substrates, stacked-die, package-on-package, flip-chip, etc. The manufacturing flow was explained in the next part, showing the economical importance of the yield at every process step. An emphasis is made on the wafer test issues, by introducing the "known-good-die" approach. Although this strategy has been used for many years in industries like avionics or aerospace, it represents a big challenge for the mass production of consumer products, where the cost is the key factor. Some emerging solutions were shown, thanks to either hardware enhancements or alternative test techniques. Packaging issues were then addressed, showing some examples of application with different configurations and their characteristics. The trends in packaging technologies demonstrate the needs for permanent innovation in this field. The final test was also discussed, posing the major problems, and describing some of their related solutions, before drawing the conclusions