Analog CMOS implementation of high frequency least-mean square error learning circuit

A continuous-time analog CMOS circuit implementing the least mean square (LMS) adaptive learning algorithm demonstrates a frequency of operation of 80MHz, an adaptivity of 60dB, a minimum notch width of 25KHz, a minimum adapt time constant of 20/spl mu/s, and the simultaneous cancellation of two CW interferers. This frequency of operation is more than an order-of-magnitude greater than that reported for previous integrated analog learning processors. This paper as also describes the first use of an auto-zero circuit to cancel offset voltages of both the integrator and multiplier circuits used for weight learning. The use of the auto zero circuit results in a 20dB higher adaptivity than obtained by previous analog adaptive processors. The high frequency learning circuitry has a number of potential applications for both conventional and neural network signal processing, especially for communication applications.