Title :
Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node
Author :
Gill, B. ; Seifert, N. ; Zia, V.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
We report on particle induced upset rates of combinational and sequential logic. A novel test chip has been designed in a 32 nm process to study the effects of single event transients (SET) and to verify the accuracy of our simulation models. The test chip has been tested under neutron and alpha particle radiation. Our measured data verify simulation-based projections that while static logic at the 32 nm technology node is sensitive to both alpha particle and neutron radiation, it is not a dominant contributor at the chip-level.
Keywords :
CMOS logic circuits; alpha-particle effects; combinational circuits; integrated circuit design; integrated circuit testing; logic design; logic testing; nanoelectronics; neutron effects; radiation hardening (electronics); sequential circuits; CMOS circuit; SET effects; alpha-particle-induced upset rate; combinational logic error rates; neutron-particle-induced upset rate; sequential logic error rates; simulation-based projection; single event transients; size 32 nm; static logic; test chip design; Alpha particles; CMOS logic circuits; Circuit simulation; Clocks; Error analysis; Logic devices; Neutrons; Single event upset; Testing; Voltage; Alpha particle; Neutron; SE; SEE; SET; combinational logic; single event effects; single-event transient; soft errors;
Conference_Titel :
Reliability Physics Symposium, 2009 IEEE International
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4244-2888-5
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2009.5173251
