A complete and automatic advanced model verification platform for 32nm technology and beyond

Author

Li, Yanfeng ; Radojcic, Riko ; Nakamoto, Mark ; Fatehi, Juzer ; Zhang, Geng ; Zhang, Xisheng ; Kang, J.F.

Author_Institution

Accelicon Technol. Inc., Cupertino, CA, USA

fYear

2009

fDate

26-30 April 2009

Firstpage

247

Lastpage

252

Abstract

Variability from different sources such as layout-dependent effect has been a main obstacle against aggressive design rule and shrinking corner margins in 45 nm node and beyond. This paper reports and demonstrates a verification platform to qualify the advanced models that address variability including layout-dependent reliability effects. This verification platform has been successfully used in real design exercise at 45 nm technology and is being applied for 32 nm technology. Test structures and methodologies of verifying different variability-aware models are presented. The platform was demonstrated to be flexible enough to account for new layout-dependent reliability behaviors in STRAIN technology.

Keywords

CMOS integrated circuits; circuit layout; circuit reliability; network synthesis; CMOS technology; automatic advanced model verification platform; layout-dependent reliability effects; size 32 nm; size 45 nm; variability-aware models; Aging; CMOS technology; Capacitive sensors; Foundries; Niobium compounds; Predictive models; SPICE; Semiconductor device modeling; Stress; Titanium compounds; DFM; NBTI; PBTI; SPICE model; TDDB; layout-dependent; model based layout extraction; strained silicon; variability-aware modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2009 IEEE International

Conference_Location

Montreal, QC

ISSN

1541-7026

Print_ISBN

978-1-4244-2888-5

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2009.5173258

Filename

5173258