Title :
250 MHz digital FIR filters for PRML disk read channels
Author :
Pearsen, D.J. ; Reynolds, S.K. ; Megdanis, A.C. ; Gowda, S. ; Wrenner, K.R. ; Immediato, M. ; Galbraith, R.L. ; Shin, H.J.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Digital FIR filters are key components of state-of-the-art partial-response signaling maximum-likelihood detection (PRML) read/write channel ICs but consume significant circuit area and power. These 10-tap and 8-tap, 6b filters provide PR-IV channel equalization at 20+MB/s data rates. Achieving these data rates while reducing power and area requires an optimized distributed arithmetic (DA) architecture combined with custom circuit design and layout. These filters improve attainable data rate by a factor of about 1.5 and power and area consumption by a factor of two, compared with standard-cell-designed filters using the same architecture and technology.
Keywords :
FIR filters; application specific integrated circuits; digital arithmetic; maximum likelihood detection; partial response channels; 20 MB/s; 250 MHz; PR-IV channel equalization; PRML disk read channels; circuit area; custom IC design; data rate; digital FIR filters; distributed arithmetic architecture; partial-response signaling maximum-likelihood detection; power consumption; Adders; Arithmetic; Circuits; Digital filters; Finite impulse response filter; Latches; Maximum likelihood detection; Shift registers; Signal detection; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535284