DocumentCode
2670664
Title
A 240 MHz 8-trap programmable FIR filter for disk-drive read channels
Author
Thon, L.E. ; Sutardja, P. ; Fang-Shi Lai ; Coleman, G.
Author_Institution
IBM Almaden Res. Center, San Jose, CA, USA
fYear
1995
fDate
15-17 Feb. 1995
Firstpage
82
Lastpage
83
Abstract
The 240 MHz digital FIR equalizer addresses the needs of magnetic disk drive applications. The FIR has low latency (3 cycles including input and output latches) to allow sufficient gain and stability in the channel timing and gain feedback loops. Programmable coefficients are supported so that the filter response can be modified in real time according to the demands of zone bit recording. (ZBR means that d is constant even as r varies in the data-rate equation.) Demands on accuracy as well as the number of taps vary, so the design is modular in the number of taps and bits to allow reuse in multiple applications. Tap counts in the range 3-10 are common. Complete testability is provided by scanmux-type static latches in all storage elements.
Keywords
CMOS digital integrated circuits; FIR filters; digital magnetic recording; programmable filters; 0.8 mum; 240 MHz; 3.7 V; 8-trap programmable FIR filter; CMOS FIR filter; channel timing; digital FIR equalizer; disk-drive read channels; filter response; gain feedback loops; high speed digital filter; low latency; magnetic disk drive applications; modular design; scanmux-type static latches; stability; testability; zone bit recording; Delay; Disk drives; Equalizers; Equations; Feedback loop; Finite impulse response filter; Magnetic separation; Stability; Testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-2495-1
Type
conf
DOI
10.1109/ISSCC.1995.535285
Filename
535285
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