DocumentCode
2670853
Title
A 0.9 V 100 MHz 4 mW 2 mm/sup 2/ 16 b DSP core
Author
Izumikawa, M. ; Igura, H. ; Furuta, K. ; Ito, H. ; Wakabayashi, H. ; Nakajima, K. ; Mogami, T. ; Horiuchi, T. ; Yamashina, M.
Author_Institution
NEC Corp., Kanagawa, Japan
fYear
1995
fDate
15-17 Feb. 1995
Firstpage
84
Lastpage
85
Abstract
A 0.25 /spl mu/m CMOS 0.9 V 100 MHz 4 mW 2 mm/sup 2/ DSP core is composed of a 16 b multiplier, a 32 b adder, an 8 kb SRAM, and a PLL. Voltage-scalable circuits capable of operating at 0.5 V to 2.5 V and level-converting interface circuits applied to the DSP make it suitable for multiple-supply-voltage portable systems.
Keywords
CMOS digital integrated circuits; digital signal processing chips; integrated circuit design; pipeline arithmetic; 0.5 to 2.5 V; 100 MHz; 16 b multiplier; 16 bit; 32 b adder; 4 mW; 8 kb SRAM; CMOS DSP core; PLL; design targets; double stage pipelined multiplier-accumulator; level-converting interface circuits; multiple-supply-voltage portable systems; voltage-scalable circuits; Adders; CMOS logic circuits; CMOS technology; Clocks; Delay effects; Digital signal processing; MOSFET circuits; Phase locked loops; Power supplies; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-2495-1
Type
conf
DOI
10.1109/ISSCC.1995.535286
Filename
535286
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