DocumentCode :
2670945
Title :
A 3D DCT architecture for compression of integral 3D images
Author :
Jalloh, I. ; Aggoun, A. ; McCormick, M.
Author_Institution :
Fac. of Comput. Sci. & Eng., De Monfort Univ., Leicester, UK
fYear :
2000
fDate :
2000
Firstpage :
238
Lastpage :
244
Abstract :
A VLSI architecture for the three-dimensional discrete cosine transform (3D DCT) is proposed. The 3D DCT is decomposed into 1D DCTs computed in each of the three dimensions. The focus of this paper is in the design of the matrix transpose required prior to the computation of the final 1D DCT which corresponds to the third dimension. This matrix transpose is divided into N memory units each performing the row-column transpose and switching networks to allow correct read and write. This architecture uses 3N multiplier-accumulators and N+1 (N×N)-words memory transpose to evaluate an (N×N×N)-point DCT at a rate of one complete 3D transform per N3 clock cycles, where N is even
Keywords :
VLSI; data compression; digital signal processing chips; discrete cosine transforms; image coding; matrix algebra; transform coding; 1D DCT; 3D DCT; 3D DCT architecture; 3D discrete cosine transform; VLSI architecture; clock cycles; integral 3D image compression; matrix transpose; memory transpose; memory units; multiplier-accumulators; row-column transpose; switching networks; Assembly; Computer architecture; Discrete cosine transforms; HDTV; Image coding; Layout; Matrix decomposition; Optical imaging; Transmission line matrix methods; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on
Conference_Location :
Lafayette, LA
ISSN :
1520-6130
Print_ISBN :
0-7803-6488-0
Type :
conf
DOI :
10.1109/SIPS.2000.886721
Filename :
886721
Link To Document :
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