DocumentCode :
2671053
Title :
114 MFLOPS logarithmic number system arithmetic unit for DSP applications
Author :
Lewis, D.M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
fYear :
1995
fDate :
15-17 Feb. 1995
Firstpage :
86
Lastpage :
87
Abstract :
Logarithmic number system (LNS) arithmetic, which represents real numbers by their logarithm in base two, offers inexpensive, error-free multiplication and division, as well as better error characteristics than floating point (FP) arithmetic, but difficult addition/subtraction. While most DSPs use fixed-point arithmetic, floating point would be attractive if it could be achieved at low cost. This paper describes an LNS core that achieves better area than contemporary FP processors. The new approach uses a function interpolator using stored function values, represented in a new interleaved ROM architecture.
Keywords :
CMOS logic circuits; arithmetic; floating point arithmetic; interleaved storage; pipeline arithmetic; signal processing; 1.2 mum; 114 MFLOPS; CMOS double well process; DSP applications; error-free division; error-free multiplication; floating point arithmetic; function interpolator; interleaved ROM architecture; logarithmic number system arithmetic unit; stored function values; Circuits; Clocks; Delay; Digital signal processing; Fixed-point arithmetic; Floating-point arithmetic; Polynomials; Read only memory; Signal generators; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
ISSN :
0193-6530
Print_ISBN :
0-7803-2495-1
Type :
conf
DOI :
10.1109/ISSCC.1995.535287
Filename :
535287
Link To Document :
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