FPGA implementation of high speed multiplierless frequency response masking FIR filters

Author

Lian, Yong

Author_Institution

Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore

fYear

2000

fDate

2000

Firstpage

317

Lastpage

325

Abstract

This paper presents the design and implementation of high speed, multiplierless, narrow transition width FIR filters using FPGA. The narrow transition width FIR filters are realized by using modified frequency response masking structure which improves the throughput rate by replacing long length filter in the original frequency response masking approach with 2 or 3 cascaded short length filters

Keywords

FIR filters; cascade networks; digital filters; field programmable gate arrays; frequency response; network synthesis; FIR filter design; FPGA implementation; Remez filter; Xilinx X4013E; cascaded short length filters; frequency response masking FIR filters; high speed multiplierless FIR filters; modified frequency response masking structure; narrow transition width FIR filters; throughput rate; Delay; Electronic mail; Field programmable gate arrays; Finite impulse response filter; Frequency response; Low pass filters; Nonlinear filters; Sampling methods; Signal processing algorithms; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on

Conference_Location

Lafayette, LA

ISSN

1520-6130

Print_ISBN

0-7803-6488-0

Type

conf

DOI

10.1109/SIPS.2000.886730

Filename

886730

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2671057