Title :
Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology
Author :
Pae, S. ; Ghani, T. ; Hattendorf, M. ; Hicks, J. ; Jopling, J. ; Maiz, J. ; Mistry, K. ; Donnell, J.O. ; Prasad, C. ; Wiedemer, J. ; Xu, J.
Author_Institution :
Logic Technol. Dev. Q&R, Intel Corp., Hillsboro, OR, USA
Abstract :
Stress induced leakage current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model and product burn-in stress data support this. With optimized process, SILC has no impact on products made of 45 nm HK+MG transistors.
Keywords :
MOSFET; leakage currents; semiconductor device reliability; thermal stability; NMOS PBTI degradation; end-of-life reliability assessment; gate stack; metal-gate transistor; nonoptimized high-K transistor; product burn-in stress data; product standby power; size 45 nm; stress induced leakage current characteristics; Degradation; Electron traps; Gate leakage; High K dielectric materials; High-K gate dielectrics; Leakage current; MOS devices; Stress; Transistors; Voltage; High-K dielectric; Metal gate; NMOS PBTI; Reliability; SILC; TDDB; Transistor;
Conference_Titel :
Reliability Physics Symposium, 2009 IEEE International
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4244-2888-5
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2009.5173303
