Variable wordlength IIR filter implementations for reduced space designs

This paper presents our work in minimizing the required space on a field programmable gate array (FPGA) for IIR digital filters. The method does not alter the filter frequency response. The assumption is that the reduced space design will naturally reduce power consumption, as well. We have used distributed look-up tables in a Xilinx XC4000 FPGA to implement our multiplications. The basis of our method is that variable wordlengths can be implemented throughout the design to reduce space without increasing output quantization noise power. Our method will work on any IIR filter type and structure, and can be used either during the design process or after the design has been completed. Our example shows that a 15%-20% reduction in space for equivalent performance is possible. One other important result of our work is that filter order alone is an inadequate measure of complexity