Fast RNS-based 2D-DCT computation on field-programmable devices

Author

Fernandez, P.G. ; Garcia, A. ; Ramirez, J. ; Lloris, A.

Author_Institution

Dept. of Electr. Eng., Jaen Univ., Spain

fYear

2000

fDate

2000

Firstpage

365

Lastpage

373

Abstract

This paper shows the implementation of an 8×8 2D-DCT (discrete cosine transform) processor based on the residue number system (RNS). It makes use of a fast cosine transform (FCT) algorithm that requires a single multiplication stage for each signal path, while most other algorithms include paths with more than one multiplication. The row-column decomposition technique is used and each 1D-DCT processor requires only 14 multipliers and 32 adders and subtractors. The proposed RNS-based 2D-DCT processor provides a throughput improvement over the equivalent 2´s complement system of up to 147% when 8-bit moduli are used. This is achieved due to the synergy between RNS and modern FPL device families

Keywords

adders; discrete cosine transforms; image coding; multiplying circuits; programmable logic devices; residue number systems; transform coding; 1D-DCT processor; 8 bit; FPL device families; RNS-based 2D-DCT processor; adders; discrete cosine transform; fast RNS-based 2D-DCT computation; fast cosine transform algorithm; field programmable logic; field-programmable devices; image compression; multiplication stage; multipliers; residue number system; row-column decomposition; signal path; subtractors; throughput; Arithmetic; Digital signal processing; Discrete cosine transforms; Discrete transforms; Dynamic range; Hardware; Image coding; Signal processing algorithms; Throughput; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on

Conference_Location

Lafayette, LA

ISSN

1520-6130

Print_ISBN

0-7803-6488-0

Type

conf

DOI

10.1109/SIPS.2000.886735

Filename

886735