VLSI implementation of a low-energy soft digital filter

Author

Hegde, Rajamohana ; Shanbhag, Naresh R.

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

2000

fDate

2000

Firstpage

437

Lastpage

446

Abstract

In this paper, we present a VLSI implementation of an energy-efficient digital filtering algorithm developed using the soft DSP framework. Soft DSP refers to overscaling the supply voltage without sacrificing speed and employing algorithmic error-control to restore the resulting performance degradation. It is shown that delay imbalance at the circuit level inherent in existing arithmetic structures results in improved energy savings with marginal degradation in performance. The proposed scheme implemented in 0.35 μm TSMC CMOS technology provides an overall energy savings of up to 76% with performance degradation of less than 1 dB in the signal-to-noise ratio (SNR₀) at the filter output

Keywords

CMOS digital integrated circuits; VLSI; digital filters; digital signal processing chips; low-power electronics; 0.35 micron; TSMC CMOS technology; VLSI implementation; algorithmic error-control; algorithmic noise tolerance; circuit level delay imbalance; energy savings; energy-efficient digital filtering algorithm; low-energy soft digital filter; signal-to-noise ratio; soft DSP framework; supply voltage overscaling; CMOS technology; Circuits; Degradation; Delay; Digital filters; Digital signal processing; Energy efficiency; Filtering algorithms; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on

Conference_Location

Lafayette, LA

ISSN

1520-6130

Print_ISBN

0-7803-6488-0

Type

conf

DOI

10.1109/SIPS.2000.886742

Filename

886742