• DocumentCode
    2671265
  • Title

    A 2-digit DBNS filter architecture

  • Author

    Eskritt, J. ; Muscedere, R. ; Jullien, G.A. ; Dimitrov, V.S. ; Miller, W.C.

  • Author_Institution
    VLSI Res. Group, Windsor Univ., Ont., Canada
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    447
  • Lastpage
    456
  • Abstract
    We have previously reported on a novel number representation using 2 bases which we refer to as the double-base number system (DBNS). Our preferred implementation uses the relatively prime bases {2,3}. If we allow the exponents of the bases to be arbitrarily large signed integers, then we can represent any real number to any arbitrary precision by a single digit DBNS representation. By representing the digit position by the exponent values, we generate a logarithmic-like representation which we can manipulate using an index calculus. A multiplier accumulator architecture for a FIR filter application has been reported which uses a half-index domain to remove the problem of addition within the index calculus. In this paper we show that using a 2-digit DBNS representation for both the input data and the filter coefficients can result in substantial hardware savings compared to both the single-digit a DBNS approach and an equivalent binary implementation of a general multiplier accumulator. In the paper we discuss the filter architecture, techniques for converting between binary and the 2-digit DBNS representations, and also the design technique used to generate the 2-digit DBNS FIR filter coefficients
  • Keywords
    FIR filters; digital arithmetic; digital filters; redundant number systems; systolic arrays; 2-digit DBNS filter architecture; FIR filter coefficients; arbitrarily large signed integers; digit position; double-base number system; half-index domain; hardware savings; index calculus; logarithmic-like representation; multiplier accumulator architecture; single digit DBNS representation; Arithmetic; Calculus; Cellular neural networks; Finite impulse response filter; Hardware; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on
  • Conference_Location
    Lafayette, LA
  • ISSN
    1520-6130
  • Print_ISBN
    0-7803-6488-0
  • Type

    conf

  • DOI
    10.1109/SIPS.2000.886743
  • Filename
    886743