Title :
Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore
Author_Institution :
Coll. of Inf. Technol., United Arab Emirates Univ., Abu Dhabi
Abstract :
This presentation discuss the many challenges faced by the design of future tera-scale integrated circuits that result from the use of nano-scale electronic devices. The relations among these challenges was studied, and a relative ranking was proposed. Afterwards, we shall delve into the most difficult challenges. Finally, possible solutions was also be suggested.
Keywords :
integrated circuit design; nanoelectronics; architectural solutions; future tera-scale integrated circuits design; nanoelectronics; nanoscale electronic devices; CMOS logic circuits; Design optimization; Josephson junctions; Logic devices; Logic testing; Nanoelectronics; Nanoscale devices; Redundancy; Single electron transistors; Space heating;
Conference_Titel :
Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on
Conference_Location :
Oslo
Print_ISBN :
0-7695-2831-7
DOI :
10.1109/ISMVL.2007.27
