Title :
A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder
Author :
Yeung, A.K. ; Rabaey, J.M.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The design of a high-speed and compact parallel add-compare-select unit using a combination of algorithmic, logic and circuit techniques is described. The results are demonstrated by a 16-state, R=1/2, 210Mb/s Viterbi decoder, that out-performs the fastest single-chip implementation previously reported by a factor of 1.8 in terms of the throughput/area metric using the same process technology.
Keywords :
CMOS logic circuits; Viterbi decoding; digital arithmetic; pipeline arithmetic; redundant number systems; 1.2 mum; 16-state Viterbi decoder; 2-metal CMOS technology; 210 Mbit/s; carry propagation free addition; dynamic logic; high-speed circuit; parallel add-compare-select unit; radix-4 bit-level pipelined Viterbi decoder; redundant number representation; single-chip implementation; throughput/area metric; Clocks; Decoding; Disk drives; Logic design; Pipeline processing; Routing; Sequences; Signal processing; Signal processing algorithms; Viterbi algorithm;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535288
