• DocumentCode
    2671308
  • Title

    Effect of chemical mechanical polishing scratch on TDDB reliability and its reduction in 45nm BEOL process

  • Author

    Liu, W. ; Lim, Y.K. ; Zhang, F. ; Zhang, W.Y. ; Chen, C.Q. ; Zhang, B.C. ; Tan, J.B. ; Sohn, D.K. ; Hsia, L.C.

  • Author_Institution
    Chartered Semicond. Manuf. Ltd., Singapore, Singapore
  • fYear
    2009
  • fDate
    26-30 April 2009
  • Firstpage
    613
  • Lastpage
    618
  • Abstract
    The correlation of time-dependent dielectric breakdown (TDDB) reliability failure with scratches generated from chemical mechanical polishing (CMP) in 45 nm backend-ofline (BEOL) process is investigated and established. The wafer map of early TDDB failure samples matches well with the defect wafer map from bright field scans. Electrical fault isolation using thermally induced voltage alteration (TIVA) analysis is employed to locate the hot spot where TDDB leakage occurs. Polish scratch induced metal damage at the hot spot is further analyzed by top down scanning electron microscopy (SEM) after de-processing. Also, the depth of the polish scratch is confirmed by using transmission electron microscopy (TEM) analysis. It clearly shows that the embedded particle on copper (Cu) surface and the liner damage resulted from polish scratch severely affect the TDDB reliability. In-situ CMP platen3 (P3) pad chemical preclean is found to reduce the polish scratch density effectively and significantly improve the V-ramp/TDDB reliability performance. However, inappropriate usage of chemical pre-clean would cause Cu corrosion and lead to EM degradation. Hence, a balance between polish scratch reduction and Cu corrosion associated with P3 pad pre-clean needs to be achieved.
  • Keywords
    chemical mechanical polishing; copper; electric breakdown; integrated circuit interconnections; integrated circuit reliability; transmission electron microscopy; BEOL process; Cu; TDDB reliability; TEM analysis; backend-ofline process; chemical mechanical polishing scratch; electrical fault isolation; polish scratch density; polish scratch induced metal; size 45 nm; thermally induced voltage alteration analysis; time-dependent dielectric breakdown reliability failure; top down scanning electron microscopy; transmission electron microscopy analysis; wafer map defect; Chemical industry; Chemical processes; Copper; Corrosion; Degradation; Dielectric breakdown; Scanning electron microscopy; Testing; Transmission electron microscopy; Voltage; CMP; TDDB; defect; polish scratch;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 2009 IEEE International
  • Conference_Location
    Montreal, QC
  • ISSN
    1541-7026
  • Print_ISBN
    978-1-4244-2888-5
  • Electronic_ISBN
    1541-7026
  • Type

    conf

  • DOI
    10.1109/IRPS.2009.5173319
  • Filename
    5173319