Title :
Yield modeling and optimization of large redundant RAMs
Author :
Ganapathy, Kumar N. ; Singh, Adit D. ; Pradhan, Dhiraj K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Presents and analyzes redundant large area TRAM architectures (64 to 512 Mbit) for variations in redundancy level and determine the optimal redundancy organization for yield enhancement. A hierarchical redundancy scheme is used for defect tolerance and the yield of the redundant RAM is modelled using a compounded Poisson model. Results are presented that show the tradeoff in local versus global redundancy schemes for TRAM
Keywords :
VLSI; integrated circuit technology; integrated memory circuits; random-access storage; redundancy; 64 to 512 Mbit; ULSI; WSI RAM; WSI memory systems; compounded Poisson model; defect tolerance; global redundancy schemes; hierarchical redundancy scheme; large area VLSI; large redundant RAMs; local redundancy schemes; multimegabit RAM; optimal redundancy organization; redundancy level; redundant large area TRAM architectures; tradeoff; tree structured RAM; yield enhancement; yield modeling; yield optimisation; Semiconductor device modeling; Switches; Switching circuits; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
DOI :
10.1109/ICWSI.1990.63911
