Low-power high-performance non-binary CMOS arithmetic circuits

Author

Lin, Rong

Author_Institution

Dept. of Comput. Sci., SUNY, Geneseo, NY, USA

fYear

2000

fDate

2000

Firstpage

477

Lastpage

486

Abstract

This paper presents several novel CMOS, low-power, high-performance arithmetic circuits for parallel counter and multiplier designs, which are developed based on a previously proposed non-binary shift switch logic scheme. Compared with the existing well-known counterpart designs, the new circuits significantly reduce power dissipation through the use of 4-bit state signals, where no more than half of the signal bits are subject to value-change at any logic stage, while achieving high speed and small VLSI area. SPICE simulations with a 0.25 micron, 2.5-V supply process have demonstrated the superiority of the circuits

Keywords

CMOS logic circuits; SPICE; VLSI; circuit simulation; counting circuits; digital arithmetic; multiplying circuits; parallel architectures; 0.25 micron; 2.5 V; 4 bit; SPICE simulations; high-performance arithmetic circuits; low-power arithmetic circuits; nonbinary CMOS arithmetic circuits; nonbinary shift switch logic; parallel counter design; parallel multiplier design; power dissipation reduction; signal bits; small VLSI area; Arithmetic; CMOS logic circuits; Counting circuits; Logic circuits; Logic design; Power dissipation; Signal design; Switches; Switching circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on

Conference_Location

Lafayette, LA

ISSN

1520-6130

Print_ISBN

0-7803-6488-0

Type

conf

DOI

10.1109/SIPS.2000.886746

Filename

886746